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FAN5069 PWM and LDO Controller Combo
September 2006
FAN5069 PWM and LDO Controller Combo
Features

Description
The FAN5069 combines a high-efficiency Pulse-WidthModulated (PWM) controller and an LDO (Low DropOut) linear regulator controller. Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET's RDS(ON) to sense current. Both the linear and PWM regulator soft-start are controlled by a single external capacitor, to limit in-rush current from the supply when the regulators are first enabled. Current limit for PWM is also programmable. The PWM regulator employs a summing-current-mode control with external compensation to achieve fast load transient response and provide design optimization. FAN5069 is offered in both industrial temperature grade (-40C to +85C) as well as commercial temperature grade (-10C to +85C).

General Purpose PWM Regulator and LDO Controller Input Voltage Range: 3V to 24V Output Voltage Range: 0.8V to 15V - VCC - 5V Shunt Regulator for 12V Operation Support for Ceramic Cap on PWM Output Programmable Current Limit for PWM Output Programmable Switching Frequency (200KHz to 600KHz) RDS(ON) Current Sensing Internal Synchronous Boot Diode Soft-Start for both PWM and LDO Multi-Fault Protection with Optional Auto-restart 16-pin TSSOP Package
Applications

PC/Server Motherboard Peripherals - VCC_MCH (1.5V), VDDQ (1.5V) and VTT_GTL (1.25V) Power Supply for - FPGA, DSP, Embedded Controllers, Graphic Card Processor, and Communication Processors Industrial Power Supplies High-Power DC-to-DC Converters
Ordering Information
Part Number
FAN5069MTCX FAN5069EMTCX
Operating Temp. Range Pb-Free
-10C to +85C -40C to +85C Yes Yes
Package
16-Lead TSSOP 16-Lead TSSOP
Packing Method
Tape and Reel Tape and Reel
Qty./Reel
2500 2500
Note: Contact Fairchild sales for availability of other package options.
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Typical Application
RVCC
+12V VCC +5V
C9
3 TO 24V
15
FAN5069
14 11
R(RAMP) BOOT
C5
R8
EN
C3
7 4 3 2 8
SS R4 R5 ILIM R(T) AGND
Q1
C4 C7
PWM
10 9
HDRV SW Q2
L1
PWM OUT
PWM OUT Q3
13 12
LDRV PGND FB
C2 C1
C6 R1
GLDO FBLDO
16 1
6
LDO OUT
C8
R7 R6
ULDO CONTROL
5
COMP
R3
R2
Figure 1. Typical Application Diagram
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Pin Assignment
FBLDO R(T ) ILIM SS COMP FB EN AGND
1 2 3 4 5 6 7 8 16 15 14
GLDO VCC R(RAMP) LDRV PGND BOOT HDRV SW
FAN5069
13 12 11 10 9
Figure 2. Pin Assignment
Pin Description
Pin #
1 2 3 4
Name
FBLDO R(T) ILIM SS
Description
LDO Feedback. This node is regulated to VREF. Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased. Current Limit. A resistor from this pin to GND sets the current limit. Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the LDO during initialization. It also sets the time by which the converter delays when restarting after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO is enabled when SS reaches 2.2V. COMP. The output of the error amplifier drives this pin. Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the feedback loop of the converter. Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and needs to be properly biased at all times. Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and drain of low-side MOSFET. High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET is turned off. Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. Power Ground. The return for the low-side MOSFET driver. Connect to the source of the lowside MOSFET. Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage feed-forward. VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. This pin has a shunt regulator which draws current when the input voltage is above 5.6V. Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
5 6 7
COMP FB EN
8 9 10
AGND SW HDRV
11 12 13
BOOT PGND LDRV
14 15
R(RAMP) VCC
16
GLDO
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings
The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation. (1)
Parameter
VCC to PGND BOOT to PGND SW to PGND HDRV (VBOOT- - VSW) LDRV All Other Pins Maximum Shunt Current for VCC Electrostatic Discharge Protection (ESD) Level(2) HBM CDM Continuous Transient (t < 50nS, F < 500kHz)
Min.
Max.
6.0 33.0
Unit
V V V V V V V mA kV
-0.5 -3.0 -0.5 -0.3 3.5 1.8
33.0 33.0 6.0 6.0 VCC + 0.3 150
Notes: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to AGND. 2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).
Thermal Information
Symbol
TSTG TL
Parameter
Storage Temperature Lead Soldering Temperature, 10 Seconds Vapor Phase, 60 Seconds Infrared, 15 Seconds
Min.
-65
Typ.
Max.
150 300 215 220 715
Unit
C C C C mW C/W C/W
PD JC JA
Power Dissipation, TA = 25C Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient
(3)
37 100
Notes: 3. Junction-to-ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat sink characteristics.
Recommended Operating Conditions
Symbol
VCC TA TJ
Parameter
Supply Voltage Ambient Temperature Junction Temperature
Conditions
VCC to GND Commercial Industrial
Min.
4.5 -10 -40
Typ.
5.0
Max.
5.5 85 85 125
Unit
V C C C
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25C, using circuit in Figure 1. The `*' denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Supply Current IVCC IVCC(SD) IVCC(OP) VSHUNT
Parameter
VCC Current (Quiescent) VCC Current (Shutdown) VCC Current (Operating) VCC Voltage(6)
Conditions
HDRV, LDRV Open EN = 0V, VCC = 5.5V EN = 5V, VCC = 5.0V, QFET = 20nC, FSW = 200kHz Sinking 1mA to 100mA at VCC Pin * * * *
Min.
2.6
Typ.
3.2 200 10
Max.
3.8 400 15 5.9
Unit
mA A mA V
5.5
Under-Voltage Lockout (UVLO) UVLO(H) Rising VCC UVLO Threshold UVLO(L) Falling VCC UVLO Threshold VCC UVLO Threshold Hysteresis Soft-Start ISS VSSOK Oscillator FOSC Frequency Frequency Range VRAMP Ramp Amplitude (Peak-to-Peak) Minimum ON Time Reference VREF Reference Voltage (Measured at FB Pin) Current Amplifier Reference (at SW node) Error Amplifier DC Gain GBWP S/R IFB Gate Drive RHUP RHDN RLUP RLDN HDRV Pull-up Resistor HDRV Pull-down Resistor LDRV Pull-up Resistor LDRV Pull-down Resistor Sourcing Sinking Sourcing Sinking * * * * 1.8 1.8 1.8 1.2 3.0 3.0 3.0 2.0 Gain-BW Product Slew Rate Output Voltage Swing FB Pin Source Current 10pF across COMP to GND No Load * 0.5 1 80 25 8 4.0 dB MHz V/S. V A TA = 0C to 70C TA = -40C to 85C * * 790 788 800 800 160 810 812 mV mV mV R(RAMP) = 330K F = 200kHz R(T) = 56K 1% R(T) = Open 240 160 160 0.4 200 300 200 360 240 600 KHz KHz KHz V nS. Current PWM Protection Enable Threshold 10 2.2 1.2 A V V VLDOSTART LDO Start Threshold 4.00 3.60 4.25 3.75 0.50 4.50 4.00 V V V
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Electrical Characteristics (Continued)
Unless otherwise noted, VCC = 5V, TA = 25C, using circuit in Figure 1. The `*' denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Protection/Disable ILIM ISWPD VUV VOV TSD
Parameter
ILIMIT Source Current SW Pull-down Current Under-Voltage Threshold Over-Voltage Threshold Thermal Shutdown Enable Threshold Voltage Enable Threshold Voltage Enable Source Current
Conditions
Min.
9
Typ.
10 2 75 115 160
Max.
11 80 120
Unit
A mA % % C V
SW = 1V, EN = 0V As % of set point; 2S noise filter As % of set point; 2S noise filter Enable Condition Disable Condition VCC = 5V * * * * * 775 770 1.17 * * 65 110
* *
2.0 0.8 50 800 800 1.2 825 830 1.23 0.3 4.5 5.3 1.2 400
V A mV mV V V V V mA A
LDO
(7)
VLDOREF
Reference Voltage (mea- TA = 0C to 70C sured at FBLDO pin) TA = -40C to 85C Regulation 0A ILOAD 5A ILOAD 5A and RDS-ON < 50m VCC = 4.75V VCC = 5.6V Gate Drive Source Current Gate Drive Sink Current
VLDO_DO Drop out Voltage External Gate Drive
Notes: 4. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 5. 6. 7. AC specifications guaranteed by design/characterization (not production tested). For a case when VCC is higher than the typical 5V VCC; voltage observed at VCC pin when the internal shunt regulator is sinking current to keep voltage on VCC pin constant. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics
Figure 3. Dead Time Waveform
Figure 6. PWM Load Transient (0 to 15A)
Figure 4. PWM Load Transient (0 to 5A)
Figure 7. LDO Load Transient (0 to 2A)
Figure 5. PWM Load Transient (0 to 10A)
Figure 8. LDO Load Transient (0 to 5A)
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)
Figure 9. PWM/LDO Power Up
Figure 12. Enable ON (IPWM = 5A)
Figure 10. PWM/LDO Power Down
Figure 13. Enable OFF (IPWM = 5A)
Figure 11. Auto Restart
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)
PWM Line Regulation (VOUT = 1.5V)
1.54
IL = 0A IL = 5A IL = 10A
1.210
LDO Load Regulation (VOUT = 1.203V)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.205
1.52
1.50
1.200
1.48
1.195
1.46 1.190 6 8 10 16 12 14 INPUT VOLTAGE (V) 18 20 0 1 2 3 LOAD CURRENT (A)
VIN = 8V VIN = 12V VIN = 15V VIN = 20V
4
5
Figure 14. PWM Line Regulation
Figure 17. LDO Load Regulation
1.210
Load Line Regulation (VOUT = 1.203V)
IL = 0A IL = 2A IL = 5A
Master Clock Frequency
700 600
OUTPUT VOLTAGE (V)
FREQUENCY (kHz)
8 10 12 14 16 INPUT VOLTAGE (V) 18 20
1.205
500 400 300 200
1.200
1.195
1.190
100 0 100 200 RT (k) 300 400
Figure 15. LDO Line Regulation
Figure 18. RT vs. Frequency
1.510
PWM Load Regulation (VOUT = 1.50V)
VIN = 8V VIN = 12V VIN = 15V VIN = 20V
Efficiency vs. Input Voltage
100
OUTPUT VOLTAGE (V)
80
1.505
EFFICIENCY (%)
60
1.500
VIN = 8V VIN = 12V VIN = 15V VIN = 20V
40
1.495 20
1.490 0 2 4 6 LOAD CURRENT (A) 8 10
0 0 2 6 4 LOAD CURRENT (A) 8 10
Figure 16. PWM Load Regulation
Figure 19. 1.5V PWM Efficiency
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Block Diagram
Vcc
Shunt Reg Internal Vcc 5.6V Max. Internal Boot Diode Current Limit Comparator
CBOOT
BOOT
10A
RILIM
ILIM
VIN
COMP FB Vref
Vcc Error Amplifier PWM Comparator
PW M
RQ S
HDRV
Adaptive Gate Drive Circuit
LO
Vout
CO
10A
OSC
SW
Current Sense Amplifier
SS
VIN
LDRV
RRAMP
Summing Ramp Generator
Amplifier Enable
R(RAMP) EN
PGND
Figure 20. Block Diagram
Detailed Operation Description
FAN5069 combines a high-efficiency, fixed-frequency PWM controller designed for single-phase synchronous buck Point-Of-Load converters with an integrated LDO controller to support GTL-type loads. This controller is ideally suited to deliver low-voltage, high-current power supplies needed in desktop computers, notebooks, workstations, and servers. The controller comes with an integrated boot diode which helps reduce component cost and increase space savings. With this controller, the input to the power supply can be varied from 3V to 24V and the output voltage can be set to regulate at 0.8V to 15V on the switcher output. The LDO output can be configured to regulate between 0.8V to 3V and the input to the LDO can be from 1.5V to 5V, respectively. An internal shunt regulator at the VCC pin facilitates the controller operation from either a 5V or 12V power source.
Choose a resistor such that:

It is rated to handle the power dissipation. Current sunk within the controller is minimized to prevent IC temperature rise.
RVCC Selection (IC)
The selection of RVCC is dependent on:

Variation of the 12V supply Gate charge of the top and bottom FETs (QFET) Switching frequency (FSW) Shunt regulator minimum current (1mA) Quiescent current of the IC (IQ)
Calculate RVCC based on the minimum input voltage for the VCC: Vin MIN - 5.6 R VCC = -----------------------------------------------------------------------------------------3 ( I Q + 1 * 10 + Q FET * F SW * 1.2 )
(EQ. 1)
VCC Bias Supply
FAN5069 can be configured to operate from 5V or 12V for VCC. When 5V supply is used for VCC, no resistor is required to be connected between the supply and the VCC. When the 12V supply is used, a resistor RVCC is connected between the 12V supply and the VCC, as shown in Figure 1. The internal shunt regulator at the VCC pin is capable of sinking 150mA of current to ensure that the controller's internal VCC is maintained at 5.6V maximum.
For a typical example, where: VinMIN = 11.5V, IQ = 3mA, QFET = 30nC, FSW = 300KHz, RVCC is calculated to be 398.65.
PWM Section
The FAN5069's PWM controller combines the conventional voltage mode control and current sensing through lower MOSFET RDS_ON to generate the PWM signals. This method of current sensing is loss-less and cost effective. For more accurate current sense requirements, an optional external resistor can be connected with the bottom MOSFET in series.
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The FAN5069 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current-sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high-side MOSFET. The sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against the voltage threshold set by the RLIM resistor to limit the inductor current on a cycle-by-cycle basis. The controller facilitates external compensation for enhanced flexibility.
age varies. The RRAMP also has an effect on the current limit, as can be seen in the RLIM equation (EQ. 5). The RRAMP value can be approximated using the following equation: V IN - 1.8 R RAMP = --------------------------------------------- K -8 6.3 * 10 * Fosc
(EQ. 4)
where FOSC is in Hz. For example, for FOSC = 300kHz and VIN = 12V, RRAMP 540K.
Gate Drive Section
The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals and provides necessary amplification, level shifting, and shoot-through protection. It also has functions that help optimize the IC performance over a wide range of operating conditions. Since the MOSFET switching time can vary dramatically from device to device and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. A low impedance path between the driver pin and the MOSFET gate is recommended for the adaptive deadtime circuit to work properly. Any delay along this path reduces the delay generated by the adaptive dead-time circuit, thereby increasing the chances for shoot-through.
Initialization
When the PWM is disabled, the SW node is connected to GND through an internal 500 MOSFET to slowly discharge the output. As long as the PWM controller is enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. The capacitor connected to the SS pin and GND is charged by a 10A internal current source, causing the voltage on the capacitor to rise. When this voltage exceeds 1.2V, all protection circuits are enabled. When this voltage exceeds 2.2V, the LDO output is enabled. The input to the error amplifier at the non-inverting pin is clamped by the voltage on the SS pin until it crosses the reference voltage. The time it takes the PWM output to reach regulation (TRise) is calculated using the following equation: T RISE = 8 x 10
-2
x C SS (CSS is in f)
(EQ. 2)
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an external resistor, connected between R(T) pin and ground. The frequency follows the graph, as shown in Figure 18. The minimum clock frequency is 200KHz, which is when R(T) pin is left open. Select the value of R(T) as shown in the equation below. This equation is valid for all FOSC > 200kHz. 5 x 10 R ( T ) = -------------------------------------------------- ( F OSC - 200 x 10 3 ) where FOSC is in Hz. For example, for FOSC = 300kHz, R(T) = 50K.
9
Protection
In the FAN5069, the converter is protected against extreme overload, short-circuit, over-voltage, and undervoltage conditions. All of these conditions generate an internal "fault latch" which shuts down the converter. For all fault conditions both the high-side and the low-side drives are off except in the case of OVP where the lowside MOSFET is turned on until the voltage on the FB pin goes below 0.4V. The fault latch can be reset either by toggling the EN pin or recycling VCC to the chip.
(EQ. 3)
Over Current Limit (PWM)
The PWM converter is protected against overloading through a cycle-by-cycle current limit set by selecting RILIM resistor. An internal 10A current source sets the threshold voltage for the output of the summing amplifier. When the summing amplifier output exceeds this threshold level, the current limit comparator trips and the PWM starts skipping pulses. If the current limit tripping occurs for 16 continuous clock cycles, a fault latch is set and the controller shuts down the converter. This shutdown fea-
RRAMP Selection and Feed-Forward Operation
The FAN5069 provides for input voltage feed-forward compensation through RRAMP. The value of RRAMP effectively changes the slope of the internal ramp, minimizing the variation of the PWM modulator gain when input volt(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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11
FAN5069 PWM and LDO Controller Combo
ture is disabled during the start-up until the voltage on the SS capacitor crosses 1.2V. To achieve current limit, the FAN5069 monitors the inductor current during the OFF time by monitoring and holding the voltage across the lower MOSFET. The voltage across the lower MOSFET is sensed between the PGND and the SW pins. The output of the summing amplifier is a function of the inductor current, RDS_ON of the bottom FET and the gain of the current sense amplifier. With the RDS_ON method of current sensing, the current limit can vary widely from unit to unit. RDS_ON not only varies from unit to unit, but also has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values). The set point of the actual current limit decreases in proportion to increase in MOSFET die temperature. A factor of 1.6 in the current limit set point typically compensates for all MOSFET RDS_ON variations, assuming the MOSFET's heat sinking keeps its operating die temperature below 125C. For more accurate current limit setting, use resistor sensing. In a resistor sensing scheme, an appropriate current sense resistor is connected between the source terminal of the bottom MOSFET and PGND. Set the current limit by choosing RILIM as follows:
11 K1 * I MAX * R DSON * 10 Vout * 33.32 * 10 1.8 R ILIM = 128 + ----------------------------------------------------------------- + 1 - -------- * --------------------------------------------------- F SW * R RAMP Vin 1.43 3
EN Pin
Pull to GND VCC Cap to GND
PWM/Restart
OFF No restart after fault Restart after TDELAY (Sec.) = 0.85 x C where C is in F
The fault latch can also be reset by recycling the VCC to the controller.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for under voltage at the FB pin. If the voltage on the FB pin stays lower than 75% of internal Vref for 16 clock cycles, the fault latch is set and the converter shuts down. This shutdown feature is disabled during startup until the voltage on the SS capacitor reaches 1.2V.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored constantly at the FB pin for over voltage. If the voltage on the FB pin stays higher than 115% of internal VREF for two clock cycles, the controller turns OFF the upper MOSFET and turns ON the lower MOSFET. This crowbar action stops when the voltage on the FB pin reaches 0.4V to prevent the output voltage from becoming negative. This over-voltage protection (OVP) feature is active as soon as the voltage on the EN pin becomes high. Turning ON the low-side MOSFETs on an OVP condition pulls down the output, resulting in a reverse current, which starts to build up in the inductor. If the output overvoltage is due to failure of the high-side MOSFET, this crowbar action pulls down the input supply or blows its fuse, protecting the system, which is very critical. During soft-start, if the output overshoots beyond 115% of VREF, the output voltage is brought down by the lowside MOSFET until the voltage on the FB pin goes below 0.4V. The fault latch is NOT set until the voltage on the SS pin reaches 1.2V. Once the fault latch is set, the converter shuts down.
115% Vref ILIM UV OV V SS >1.2V S Q 0.4V R LS Drive
EN
(EQ. 5)
where RILIM is in K. IMAX is the maximum load current. K1 is a constant to accommodate for the variation of MOSFET RDS(ON) (typically 1.6). With K1 = 1.6, IMAX = 20A, RDS(ON) = 7m, VIN = 24V, VOUT = 1.5V, FSW = 300 KHz, RRAMP = 400 K, RILIM calculates to be 323.17K.
Auto Restart (PWM)
The FAN5069 supports two modes of response when the internal fault latch is set. The user can configure it to keep the power supply latched in the OFF state OR in the Auto Restart mode. When the EN pin is tied to VCC, the power supply is latched OFF. When the EN pin is terminated with a 100nF to GND, the power supply is in Auto Restart mode. The table below describes the relationship between PWM restart and setting on EN pin. Do not leave the EN pin open without any capacitor.
S Q R
Fault Latch
FB
Delay 2 Clks
Figure 21. Over-Voltage Protection
Thermal Fault Protection
The FAN5069 features thermal protection where the IC temperature is monitored. When the IC junction temperature exceeds +160C, the controller shuts down and when the junction temperature gets down to +125C, the converter restarts.
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FAN5069 PWM and LDO Controller Combo
LDO Section
The LDO controller is designed to provide ultra low voltages, as low as 0.8V for GTL-type loads. The regulating loop employs a very fast response feedback loop and small capacitors can be used to keep track of the changing output voltage during transients. For stable operation, the minimum capacitance on the output needs to be 100F and the typical ESR needs to be around 100m. The maximum voltage at the gate drive for the MOSFET can reach close to 0.5V below the VCC of the controller. For example, for a 1.2V output, the minimum enhancement voltage required with 4.75V on VCC is 3.05V (4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the LDO is dependent on the load current and the MOSFET chosen. It is recommended to use low enhancement voltage MOSFETs for the LDO. In applications where LDO is not needed, pull up the FBLDO pin (Pin #1) higher than 1V to disable the LDO. The soft-start on the LDO output (ramp) is controlled by the capacitor on the SS pin to GND. The LDO output is enabled only when the voltage on the SS pin reaches 2.2V. Refer to Figure 9 for start-up waveform.
operate at the boundary of continuous and discontinuous conduction modes.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V. The output voltage of the PWM regulator can be set in the range of 0.8V to 90% of its power input by an external resistor divider. The output is divided down by an external voltage divider to the FB pin (for example, R1 and RBIAS as in Figure 24). The output voltage is given by the following equation: R1 V OUT = 0.8V x 1 + --------------- R BIAS
(EQ. 6)
To minimize noise pickup on this node, keep the resistor to GND (RBIAS) below 10K.
Inductor Selection (PWM)
When the ripple current, switching frequency of the converter, and the input-output voltages are established, select the inductor using the following equation: V OUT V - -------------- OUT V IN = ------------------------------------------I Ripple x F SW
2
Design Section
General Design Guidelines
Establishing the input voltage range and maximum current loading on the converter before choosing the switching frequency and the inductor ripple current is highly recommended. There are design trade-offs in choosing an optimum switching frequency and the ripple current. The input voltage range should accommodate the worstcase input voltage with which the converter may ever operate. This voltage needs to account for the cable drop encountered from the source to the converter. Typically, the converter efficiency tends to be higher at lower input voltage conditions. When selecting maximum loading conditions, consider the transient and steady-state (continuous) loading separately. The transient loading affects the selection of the inductor and the output capacitors. Steady state loading affects the selection of MOSFETs, input capacitors, and other critical heat-generating components. The selection of switching frequency is challenging. While higher switching frequency results in smaller components, it also results in lower efficiency. Ideal selection of switching frequency takes into account the maximum operating voltage. The MOSFET switching losses are directly proportional to FSW and the square function of the input voltage. When selecting the inductor, consider the minimum and maximum load conditions. Lower inductor values produce better transient response, but result in higher ripple and lower efficiency due to high RMS currents. Optimum minimum inductance value enables the converter to
L MIN
(EQ. 7)
where IRipple is the ripple current. This number typically varies between 20% to 50% of the maximum steady-state load on the converter. When selecting an inductor from the vendors, select the inductance value which is close to the value calculated at the rated current (including half the ripple current).
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS current rating to withstand the temperature rise caused by the internal power dissipation. The combined RMS current rating for the input capacitor should be greater than the value calculated using the following equation: V OUT V OUT 2 I INPUT ( RMS ) = I LOAD ( MAX ) x -------------- - -------------- (EQ. 8) V IN V IN Common capacitor types used for such application include aluminum, ceramic, POS CAP, and OSCON.
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough ESR to meet the output ripple and load transient requirements. The ESR of the output capacitor should be lower than both of the values calculated below to satisfy both the transient loading and steady-state ripple conditions as given by the following equation: V STEP ESR --------------------------------- and I LOAD ( MAX ) V Ripple ESR -----------------I Ripple
(EQ. 9)
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
In the case of aluminum and polymer based capacitors, the output capacitance is typically higher than normally required to meet these requirements. While selecting the ceramic capacitors for the output; although lower ESR can be achieved easily, higher capacitance values are required to meet the VOUT(MIN) restrictions during a load transient. From the stability point of view, the zero caused by the ESR of the output capacitor plays an important role in the stability of the converter.
5V CGD RD HDRV RGATE G CGS SW
VIN
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100F with ESR around 100m is recommended. For other values, contact the factory.
Figure 23. Drive Equivalent Circuit The upper graph in Figure 22 represents Drain-toSource Voltage (VDS) and Drain Current (ID) waveforms. The lower graph details Gate-to-Source Voltage (VGS) vs. time with a constant current charging the gate. The xaxis is representative of Gate Charge (QG). CISS = CGD + CGS and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). Obtain the gate charge (QG) parameters shown on the lower graph from the MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12): PUPPER = PSW + PCOND V DS x I L P SW = --------------------- x 2 x t s F SW 2 V OUT 2 P COND = -------------- x I OUT x R DS ( ON ) V IN
(EQ. 10) (EQ. 11)
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs as circuit switch elements. For better performance, MOSFET selection must address these key parameters: maximum Drain-to-Source Voltage (VDS) should be at least 25% higher than worst-case input voltage. The MOSFETs should have low QG, QGD, and QGS. The RDS_ON of the MOSFETs should be as low as possible. In typical applications for a buck converter, the duty cycles are lower than 20%. To optimize the selection of MOSFETs for both the high-side and low-side, follow different selection criteria. Select the high-side MOSFET to minimize the switching losses and the low-side MOSFET to minimize the conduction losses due to the channel and the body diode losses. Note that the gate drive losses also affect the temperature rise on the controller. For loss calculation, refer to Fairchild's Application Note AN-6005 and the associated spreadsheet.
The
(EQ. 12)
High-Side Losses
Losses in the MOSFET can be understood by following the switching interval of the MOSFET in Figure 22. MOSFET gate drive equivalent circuit is shown in Figure 23.
CISS VDS CGD CISS
where PUPPER is the upper MOSFET's total losses and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ) and tS is the switching period (rise or fall time) and equals t2+t3 (Figure 22.). The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP, assume a constant current for the driver to simplify the calculation of tS using the following equation: Q G ( SW ) Q G ( SW ) t s = ------------------- --------------------------------------------I Driver V CC - V SP --------------------------------------- R Driver + R Gate
(EQ. 13)
ID
Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as:
QGS VSP VTH QGD
4.5V
QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to reach the MOSFET threshold (VTH). Note that for the high-side MOSFET, VDS equals VIN, which can be as high as 20V in a typical portable application. Include the power delivered to the MOSFET's (PGATE) in calculating the power dissipation required for the FAN5069.
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VGS
t1 t2
QG(SW)
t3 t4 t5
Figure 22. Switching Losses and QG
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
PGATE is determined by the following equation: P Gate = Q G x V CC x F SW where QG is the total gate charge to reach VCC.
(EQ. 14)
R-C components for the snubber are selected as follows: a) Measure the SW node ringing frequency (Fring) with a low capacitance scope probe. b) Connect a capacitor (CSNUB) from SW node to GND so that it reduces this ringing by half. c) Place a resistor (RSNUB) in series with this capacitor. RSNUB is calculated using the following equation: 2 R SNUB = ---------------------------------------------(EQ. 17) x F ring x C SNUB d) Calculate the power dissipated in the snubber resistor as shown in the following equation: P R ( SNUB ) = C SNUB x V IN ( MAX ) x F SW
2
Low-Side Losses
Q2 switches on or off with its parallel schottky diode simultaneously conducting, so the VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and Q2 is selected based on RDS(ON) alone. Conduction losses for Q2 are given by the equation: 2 (EQ. 15) P COND = ( 1 - D ) x I OUT x R DS ( ON ) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and D=VOUT/VIN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the lowside MOSFET, the JA, and the maximum allowable ambient temperature rise. PD(MAX) is calculated using the following equation: T J ( MAX ) - T A ( MAX ) P D ( MAX ) = ----------------------------------------------- JA
(EQ. 16)
(EQ. 18)
where, VIN(MAX) is the maximum input voltage and FSW is the converter switching frequency. The snubber resistor chosen should be de-rated to handle the worst-case power dissipation. Do not use wirewound resistors for RSNUB.
Loop Compensation
Typically, the closed loop crossover frequency (Fcross), where the overall gain is unity, should be selected to achieve optimal transient and steady-state response to disturbances in line and load conditions. It is recommended to keep Fcross below fifth of the switching frequency of the converter. Higher phase margin tends to have a more stable system with more sluggish response to load transients. Optimum phase margin is about 60, a good compromise between steady state and transient responses. A typical design should address variations over a wide range of load conditions and over a large sample of devices.
JA depends primarily on the amount of PCB area devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switching transitions due to the energy stored in the parasitic elements. This ringing on the SW node couples to other circuits around the converter if they are not handled properly. To dampen this ringing, an R-C snubber is connected across the SW node and the source of the lowside MOSFET.
VIN
Current Sense Amplifier
VIN
Q1 L RDC C RES VOUT RL
RRAMP
Ramp Generator Summing
Amplifier
PWM & DRIVER
Q2
C2 C1 RBIAS
Reference
R2
C3 R1
R3
Figure 24. Closed-Loop System with Type-3 Network
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
FAN5069 has a high gain error amplifier around which the loop is closed. Figure 24 shows a Type-3 compensation network. For Type-2 compensation, R3 and C3 are not used. Since the FAN5069 architecture employs summing current mode, Type-2 compensation can be used for most applications.
For further information about Type-2 compensation networks, refer to:
Venable, H. Dean, "The K factor: A new mathematical tool for stability analysis and synthesis," Proceedings of Powercon, March 1983.
Note: For critical applications requiring wide loop bandwidth using very low ESR output capacitors, use Type-3 compensation. Type 3 Feedback Component Calculations Use the following steps to calculate feedback components: Notation: C 0 = Net Output Filter capacitance G p ( s ) = Net Gain of Plant = control-to-output transfer function L = Inductor Value R DSON = ON-state Drain-to Source Resistance of Low-side MOSFET R es = Net ESR of the Output Filter Capacitors R L = Load Resistance T s = Switching Period V IN = Input Voltage F SW = Switching Frequency
Equations:
Effective current sense resistance = R i = 7 x R DSON RL Current modulator DC gain = M i = -----Ri ( V IN - 1.8 ) x T s Effective ramp amplitude = V m = 3.33 x 10 10 x ---------------------------------------R ramp
(EQ. 21) (EQ. 19)
(EQ. 20)
V IN Voltage modulator DC gain = M v = -------Vm Mv x Mi Plant DC gain = M o = M v || M i = ------------------Mv + Mi Sampling gain natural frequency = n = ----Ts -2 Sampling gain quality factor (damping) = Q z = ---- MO Mv x Ri Effective inductance = L e = -------- x L + ------------------- Mv n x Q z Mv x Ri x RL R p = -------------------------------- = ( M v x R i ) || R L Mv x Ri + RL
(EQ. 22)
(EQ. 23)
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Poles and Zeros of Plant Transfer Function:
1 Plant zero frequency = f z = ----------------------------------------2 x x C o x R es 1 Plant 1st pole frequency = f p1 = ---------------------------------------------------------Le - 2 x x C o x R p + ------ RL Rp 1 1 Plant 2nd pole frequency = f p2 = ------------ x ------------------- + ------ Co x RL Le 2x n x Le Plant 3rd pole frequency = f p3 = ------------------------2 x x Rp
2
(EQ. 28)
(EQ. 29)
(EQ. 30)
(EQ. 31)
Plant gain (magnitude) response:
f2 1 + --- f z G p (f) = 20 x log M 0 + 10 x log --------------------------------------------------------------------------------------------------------f2 f2 f2 - - - 1 + ------ x 1 + ------ x 1 + ------ f p1 f p2 f p3
(EQ. 32)
Plant phase response:
-1 f -1 f -1 f -1 f G P (f) = tan --- - tan ------ - tan ------ - - tan ------ f z f p1 f p2 f p3
(EQ. 33)
Choose R1, RBIAS to set the output voltage using EQ.6. Choose the zero crossover frequency Fcross of the overall loop. Typically Fcross should be less than fifth of Fsw. Choose the desired phase margin; typically between 60 to 90. Calculate plant gain at Fcross using EQ.34 by substituting Fcross in place of f. The gain that the amplifier needs to provide to get the required crossover is given by: 1 (EQ. 34) G AMP = ------------------------------G p (F cross ) The phase boost required is calculated as given in (EQ. 35) Phase Boost = M - G P (F cross ) - 90 where M is the desired phase margin in degrees. The feedback component values are calculated as given in equations below: Boost K = Tan --------------- + 45 4 -
2
(EQ. 35)
(EQ. 36)
1 C2 = ----------------------------------------------------------------------2 x x F cross x G AMP x R1 C1 = C2 x ( K - 1 ) 1 C3 = --------------------------------------------------------------2 x x F cross x K x R3 K R2 = ------------------------------------------------2 x x F cross x C1 R1 R3 = ----------------(K - 1)
(EQ. 37) (EQ. 38) (EQ. 39)
(EQ. 40)
(EQ. 41)
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Design Tools
Fairchild application note AN-6010 provides a PSPICE model and spreadsheet calculator for the PWM regulator, simplifying external component selections and verifying loop stability. The topics covered provide an understanding of the calculations in the spreadsheet. The spreadsheet calculator, which is part of AN-6010, can be used to calculate all external component values for designing around FAN5069. The spreadsheet provides optimized compensation components and generates a Bode Plot to ensure loop stability. Based on the input values entered, AN-6010's PSPICE model can be used to simulate Bode Plots (for loop stability) as well as transient analysis to help customize the design for a wide range of applications. Use Fairchild Application Note AN-6005 for prediction of the losses and die temperatures for the power semiconductors used in the circuit. AN-6010 and AN-6005 can be downloaded from www.fairchildsemi.com/apnotes/.
Layout Considerations
The switching power converter layout needs careful attention and is critical to achieving low losses and clean and stable operation. Below are specific recommendations for good board layout:

Keep the high-current traces and load connections as short as possible. Use thick copper boards whenever possible to achieve higher efficiency. Keep the loop area between the SW node, low-side MOSFET, inductor, and the output capacitor as small as possible. Route high dV/dt signals, such as SW node, away from the error amplifier input/output pins. Keep components connected to these pins close to the pins. Place ceramic de-coupling capacitors very close to the VCC pin. All input signals are referenced with respect to AGND pin. Dedicate one layer of the PCB for a GND plane. Use at least four layers for the PCB. Minimize GND loops in the layout to avoid EMI-related issues. Use wide traces for the lower gate drive to keep the drive impedances low. Connect PGND directly to the lower MOSFET source pin. Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFETs. Use snubber circuits to minimize high-frequency ringing at the SW nodes. Place the output capacitor for the LDO close to the source of the LDO MOSFET.
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Application Board Schematic
VIN = 3 to 24V; VOUT =1.5V at 20A.
+5V or +12V Vcc J1 R9 220 PWM OUT C7 0.22F 15 Q1 FDD6530A VCC U1 3-24V R(RAMP) 14 R6 453K FDD6296 16 GLDO HDRV 10 Q2 C6 0.1F C10 + C11 + 820F J2 VIN J3 GND
LDO
820F
J7 LDO_Out C4 0.1F J6 GND C17 + 560F
R8 5K R7 10K R4 50K R5 243K C5 TP1
1
FBLDO
BOOT
11 C8 0.22F
PWM OUT
L1 FDD6606 Q4
1.8H
2
R(T)
SW
9 FDD6606 R11 2.2 C12 + C13 + C14 + C15 0.1F
J4 SW_Out
3
IL IM
LDRV
13
Q3
560F 560F 560F C16 3.3nF
4 0.1F TP2 C9 0.01F 8 7
SS
PGND
12 C1 1500pF
J5 GND C3
EN
COMP
5 C2 220pF
R2 12.7k
R3 825 R1 5.11K
3300pF
AGND FAN5069
FB
6
R10
5.83K
Figure 25. Application Board Schematic
Bill of Materials
Part Description
Capacitor, 1500pF, 20%, 25V, 0603,X7R Capacitor, 220pF, 5%, 50V, 0603,NPO Capacitor, 3300pF, 10%, 50V, 0603,X7R Capacitor, 0.1F, 10%, 25V, 0603,X7R Capacitor, 0.22F, 20%, 25V, 0603,X7R Capacitor, 0.01F, 10%, 50V, 0603,X7R Capacitor, 820F, 20%, 10X20, 25V,20mOhm,1.96A Capacitor, 820F, 20%, 8X8, 2.5V,7mOhm,6.1A Capacitor, 560F, 20%, 8X11.5, 4V,7mOhm,5.58A Capacitor, 3300pF, 10%, 50V, 0603,X7R Connector Header 0.100 Vertical, Tin - 2 Pin Terminal Quickfit Male .052"Dia.187" Tab Inductor, 1.8H, 20%, 26Amps Max, 3.24mOhm MOSFET N-CH, 32 m, 20V, 21A, D-PAK, FSID: FDD6530A MOSFET N-CH, 8.8 m, 30V, 50A, D-PAK, FSID: FDD6296 MOSFET N-CH, 6 m, 30V, 75A, D-PAK, FSID: FDD6606 Resistor, 5.11K, 1%, 1/16W Resistor, 12.7K, 1%, 1/16W Resistor, 825, 1%, 1/16W Resistor, 49.9K, 1%, 1/16W Resistor, 243K, 1%, 1/16W Resistor,453K, 1%, 1/16W Resistor,10K, 1%, 1/16W Resistor, 4.99K, 1%, 1/16W Resistor, 220, 1%, 1/4W Resistor, 5.90K, 1%, 1/16W Resistor, 2.2, 1%, 1/4W Connector Header 0.100 Vertical, Tin - 1 Pin IC, System Regulator, TSSOP16, FSID: FAN5069
Quantity
1 1 1 4 2 1 2 1 3 1 1 6 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 3 1
Designator
C1 C2 C3 C4, C5, C6, C15 C7, C8 C9 C10, C11 C17 C12, C13, C14 C16 J1 J2 - J7 L1 Q1 Q2 Q3, Q4 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 TP1,TP2, Vcc U1
Vendor
Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Nippon-Chemicon Nippon-Chemicon Nippon-Chemicon Panasonic Molex Keystone Inter-Technical Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Molex Fairchild Semiconductor
Vendor Part #
PCC1774CT-ND PCC221ACVCT-ND PCC1778CT-ND PCC2277CT-ND PCC1767CT-ND PCC1784CT-ND KZH25VB820MHJ20 PSC2.5VB820MH08 PSA4VB560MH11 PCC332BNCT-ND WM6436-ND 1212K-ND SC5018-1R8M FDD6530A FDD6296 FDD6606 P5.11KHCT-ND P12.7KHCT-ND P825HCT-ND P49.9KHCT-ND P243KHCT-ND P453KHCT-ND P10.0KHCT-ND P4.99KHCT-ND P200FCT-ND P5.90KHCT-ND P2.2ECT-ND WM6436-ND FAIRCHILD
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Typical Application Board Layout
Figure 26. Assembly Diagram
Figure 29. Mid Layer 2
Figure 27. Top Layer
Figure 30. Bottom Layer
Figure 28. Mid Layer 1
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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FAN5069 PWM and LDO Controller Combo
Mechanical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 31. 16-Lead TSSOP
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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21
FAN5069 PWM and LDO Controller Combo
(c) 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5
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